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d여기에서 PCIe QuickLearn | PCIe Overview: Data – mindshare pcie training 주제에 대한 세부정보를 참조하세요
Purpose:
This 5-minute video provides the viewer with the fundamental concepts related to PCIe; it is the first video in a series that focuses primarily on the clocks and timing issues related to PCIe, and it also provides a basic understanding with which to explore further PCIe topics.
Intended Audience:
Anyone interested in an easy-to-understand high-level introduction to PCIe. No prior knowledge of PCIe is assumed.
What topics are covered?
1. Point-to-Point bus
2. Bi-directional bus
3. Scalability of data rates
4. Backwards compatibility
5. Wide adoption across many markets
6. Typical PCIe clock format
For more information, please visit:
https://www.microchip.com/PCIeTiming
mindshare pcie training 주제에 대한 자세한 내용은 여기를 참조하세요.
PCI Express System Architecture – MindShare – PDF4PRO
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- Author: Microchip Technology
- Views: 조회수 13,351회
- Likes: 좋아요 213개
- Date Published: 2020. 12. 1.
- Video Url link: https://www.youtube.com/watch?v=VWNAqEYOy7g
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PCI Express System Architecture – MindShare
Training that fi ts your needsMindShare recognizes and addresses your company s technical training issues with: Scalable cost training Customizable training options Reducing time away from work Just-in-time training Overview and advanced topic courses Training delivered effectively globally Training in a classroom, at your cubicle or home offi ce Concurrently delivered multiple-site trainingbringing lifeto knowledge. real-world tech training put into practice worldwide real-world tech training put into practice worldwide real-world tech training put into practice worldwide real-world tech training put into practice worldwideAre your company s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge technologies. We understand the challenges companies have when searching for quality, effective training which reduces the students time away from work and provides cost-effective alternatives.
PCI Express System Architecture MINDSHARE, INC. Ravi Budruk Don Anderson Tom Shanley Technical Edit by Joe Winkles ADDISON-WESLEY DEVELOPER’S PRESS Boston • San Francisco • New York • Toronto
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Documents from same domain SAS Storage Architecture – MindShare www.mindshare.com training that fi ts your needs MindShare recognizes and addresses your company’s technical training issues with: • Scalable cost training • Customizable training options • Reducing time away from work • Just-in-time training • Overview and advanced topic courses • Training delivered effectively globally • Training in a classroom, at your cubicle or home offi ce … x86 Instruction Set Architecture – MindShare www.mindshare.com At-a-Glance Table of Contents Part 1: Introduction, intended as a back-drop to the detailed discussions that follow, consists of the following chapters: † Chapter 1, “Basic Terms and Concepts,” on page 11. PCI Express PIPE Overview – MindShare www.mindshare.com internal logic referred to in the spec as the Media Access Layer (MAC). The MAC in turn connects to the PCI Express Data Link Layer logic. The PIPE spec builds on the PCI Express base spec, so it should be noted that a working knowledge of that document is essential for a good understanding of the PIPE spec.
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PCI Express For Software Engineers Training PDF documents
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[email protected] Express for Software EngineersTrainingLet MindShare Bring “PCI Express for Software Engineers” To Life For YouMindShare’s PCI Express for Software Engineers course starts with a high-level view of the technology toprovide the big-picture context of PCIe protocol. The course then describes configuration space and theenumeration process. The most important registers are described including those related to error andinterrupt handling.The course describes registers added with each generation of specification from PCIe specification 1.1 tothe latest 5.0. There are a large number of features and optional behaviors described in the PCIe spec.MindShare can customize the course to cover the topics that are most important for your group. Use thecourse outline below as a guide to request topics you want covered or removed.You Will Learn: PCI Express features and capabilitiesThe definition and responsibilities of each of the layers in the interfaceOverview of the PCIe packet-based transaction protocolThe error detection, reporting and possible correction mechanismsThe address space and packet-routing methods usedHow the various power management techniques workThe details of the configuration registers that provide control and status visibility to softwareSoftware enumeration processOverview of the equalization necessary to operate at 8.0GT/s and higher speedsOverview the LTSSM including the concepts important for each stateEssential features added to Gen3, Gen4 and Gen5 specificationsFor SRIOV and ATS related topics, which are incorporated into the PCIe 5.0 spec, please request our 3-dayIO Virtualization for Intel Platforms or IO Virtualization for ARM Platforms as these topics are NOT coveredin this standard 5-day PCIe course. Additionally, PIPE 6.0 spec related topics are not covered but can beadded upon request. Some of the ECNs listed below are covered upon request.Who Should Attend?This course is suitable for software engineers because the configuration registers used to control thehardware are covered in detail. Firmware and device driver coders will benefit from understanding theenumeration process and learning the function of the most important PCIe registers.Course Length: 3 Days (but customizable to shorter or longer duration)Course Outline:Hands-On Software5-day Class 3-day ClassPCI Architecture Background FoundationPCI concepts important for understanding PCI ExpressXXPhysical Address SpacesXXTraffic Types (System Memory, PIO and DMA)XXTypical System Transactions (NVMe Example)XX [email protected] Software5-day Class 3-day ClassPCI Express Features and Architecture OverviewLayered ArchitectureXXARM example topologyXXTLP, DLLP and Ordered Set Packet Format OverviewXXProtocol OverviewXXLegacy and Enhanced Configuration Access Mechanism (ECAM)Type 0 and Type 1 Headers, Capability and Extended CapabilityStructuresBus EnumerationXXXXXXHANDS-ON ARBOR LAB: Scan your system and determine topologyXXClarification of Memory spaceXXSystem memory vs MMIOXXPrefetchable vs Non-prefetchableXXIO spaceXXSetting up the BARs as well as the Base and Limit registersXXSwitch Routing MechanismXXHANDS-ON ARBOR LAB: Debug problem with address mappingXXNormal TLP fieldsXoverviewTLP PrefixesXLightweight Notification and TPH / Steering TagsX10-bit TagsXPCI-SIG Vendor-Defined MessagesXConfiguration OverviewAddress Space and Transaction RoutingTLP Format DetailsoverviewQuality of Service and ArbitrationTC/VC MappingXoverviewVC ArbitrationXoverviewPort ArbitrationXoverviewMulti-function ArbitrationXoverviewFlow Control ProtocolXoverviewScaled Flow ControlXoverviewLink Feature ExchangeXoverviewFlow Control InitializationXoverviewRuntime Flow Control Update MechanismXoverviewFlow Control [email protected] Software5-day Class 3-day ClassTransaction OrderingSimplified Ordering TableRelaxed and ID-Based OrderingXXXXDLLP Format DetailsDLLPsXNOP & Data Link Feature DLLPsXACK / NAK ProtocolTLP Error Recovery MechanismXoverviewSimplified Replay TimerXXExamples of Numerous Error ScenariosXNullified Packets and Cut-Through Mode SwitchesXoverviewBlock DiagramXoverviewOrdered SetsXByte Striping/UnstripingXScrambling/UnscamblingX8b/10b al Layer Logic (2.5GT/s and 5.0GT/s)Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s)128b/130b Encoding/DecodingXoverviewControl SKPsXOrdered-Set Blocks and Data BlocksXData Streams and Packet FramingXData Parity CheckingXoverview16.0 & 32.0 GT/s Data Parity CheckingXoverviewPrecodingXoverviewPhysical Layer Electrical (all speeds)Differential Tx / RxX2.5GT/s and 5.0GT/s De-emphasisXoverview8.0GT/s, 16.0GT/s and 32.0GT/s Equalization ConceptXoverviewRx EqualizationXElectrical Conditions for different Link StatesXSpread Spectrum Clocking (SSC)XSeparate Refclk Independent SSC (SRIS)X [email protected] Software5-day Class 3-day ClassLink Initialization and Training (LTSSM)Detect, Polling, Configuration, L0 StatesXoverviewRecovery: Link Speed ChangeXoverviewRecovery: Equalization ProcessXoverview16.0 GT/s Equalization and Config StructuresXoverviewNegotiation for skipping parts or all of Tx EqualizationXoverview32.0 GT/s Equalization and Config StructuresXoverviewL0s, L1, L2, Hot Reset, Link Disable and Loopback StatesXoverviewModified TS1 / TS2s and Alternate Protocol NegotiationXoverviewMSI InterruptsXX32-bit MSI DataXXMSI-X InterruptsHANDS-ON ARBOR LAB: Investigate source of MSI(-X) interrupt anddeliveryXXXXCorrectable, Non-Fatal and Fatal ErrorsXXAdvisory Non-Fatal ErrorsXXXXXXDevice Power StatesXXLink Power StatesXXL1 SubstatesXoverviewActive State Power Management (ASPM) – hardware controlledXoverviewSoftware Controlled Power ManagementXoverviewPower Management Events (PME, Beacon and #WAKE)XRecovery: Link Width ChangeInterrupt SupportLegacy Interrupt HandlingError Detection and HandlingError Subclass field for Correctable Error MessagesAdvanced Error Reporting (AER)HANDS-ON ARBOR LAB: Determine source and error reportingmechanismPower ManagementLink ActivationDynamic Power Allocation (DPA)Optimized Buffer Flush Fill (OBFF)Latency Tolerance Reporting (LTR)XXConventional Reset Mechanisms: Cold, Warm and Hot ResetXXFunction Level Reset (FLR)XXSystem Resets [email protected] Software5-day Class 3-day ClassFeatures Introduced with PCIe 4.0RetimersoverviewoverviewLane MarginingoverviewoverviewFlattening Portal Bridge archy ID ReportingDesignated Vendor-Specific Extended Capability (DVSEC)Enhanced AllocationEmergency Power Reduction StateFeatures Introduced with PCIe 5.0System Firmware Intermediary SupportOther PCIe Features (ECNs)Hot PlugPower BudgetingMulti-CastingProtocol Multiplexing (PMUX)Resizable BARsDownstream Port Containment (DPC) and Enhanced DPC (eDPC)Lightweight Notification (can be used for lightweight cache coherency)Process Address Space ID (PASID)Precision Time Measurement (PTM)Device Readiness Status (DRS) and Function Readiness Status (FRS)Recommended Prerequisites:A basic understanding of digital bus architectures such as PCI is recommended.Course Material:1) PCI Express Technology eBook (or hardcopy on request) by Mike Jackson and Ravi Budruk2) Downloadable PDF version of the presentation slides3) Add-On MindShare Arbor software tool, used for student labs in the class (discounted pricing applies)4) Add-On Comprehensive PCI Express eLearning course (discounted pricing applies)800-633-1440 1-800-633-1440 www.mindshare.com [email protected] Hands-On 5-day Class Software 3-day Class PCI Express Features and Architecture Overview Layered Architecture X X ARM example topology X X TLP, DLLP and Ordered Set Packet Format
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